1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a wordline driver for a semiconductor memory device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a driving voltage in the semiconductor memory device.
2. Discussion of the Related Art
When a row decoder decodes an externally applied row address in a semiconductor memory device, a wordline driver drives a wordline in accordance with a signal outputted from the row decoder. As a more integrated memory device is required, a design rule of the wordline becomes smaller. Also, the number of cells driven by a single wordline is increased with this trend.
To satisfy such demand, a dual wordline decoding scheme (DWDS) has been introduced. A wordline of the DWDS is divided by main wordlines and sub-wordlines and driven by hierarchically decoding a row address.
FIG. 1 is a block diagram of a dual wordline driver (DWD) in accordance with a background art. Specifically, the DWD includes a row decoder RD 10 decoding an externally inputted row address and outputting a main decoding signal. A plurality of wordline drive decoders WDD 20 each decoding two lowest bits among row address signals and outputting a sub-decoding signal. A plurality of sub-wordline drivers SWD 30 driving sub-wordlines using the main decoding signal from the row decoder RD 10 and the sub-decoding signals from the wordline drive decoders WDD 20.
The wordline drive decoders WDD 20 and the sub-wordline drivers SWD 30 are hierarchically connected each other. A plurality of cell arrays divided by a bitline sensing amplifier (BLSA) constitute a single bank.
FIG. 2 is a detailed diagram illustrating a part of the wordline driver for the semiconductor memory device.
FIG. 3 illustrates a circuit diagram of a single sub-wordline driver SWD 30. As shown therein, the sub-wordline driver SWD 30 includes a PMOS transistor P1 having a gate receiving an inverted main decoding signal MWLb and a source receiving a sub-decoding signal Wdi. An NMOS transistor N1 are connected between a drain of the PMOS transistor P1 and a ground Vss and having a gate receiving the inverted main decoding signal MWLb. A second NMOS transistor N2 are connected in parallel between the source and drain of the PMOS transistor P1 and having a gate receiving a main decoding signal MWL.
Each drain of the PMOS transistor P1 and the first NMOS transistor N1 and the source of the second NMOS transistor N2 are connected with a sub-wordline SWL through an output node A.
The operation of the wordline driver for the semiconductor memory device will be described as follows.
When a row address signal is externally inputted, as shown in FIG. 2, each pair of the wordline drive decoders WDD 20 respectively outputs four decoding signals WDi by decoding the two lowest bits among input row address signals. The row decoder RD 10 outputs the main decoding signals MWL and MWLb in accordance with a remaining row address signal.
Accordingly, the plurality of sub-wordline drivers SWD 30 enable each corresponding the sub-wordlines SWL in accordance with each level of the main decoding signals MWL, MWLb and the decoding signals WDi from the wordline drive decoder WDD 20.
Specifically, as shown in FIGS. 4A through 4D, only the first NMOS transistor N1 of the sub-wordline driver 30 is turned on for a period t1, thus a signal transmitted to the sub-wordline SWL through the output node A becomes a low level. For a period t2, the sub-wordline SWL is maintained in the low level. The second NMOS transistor N2 and the PMOS transistor P1 of each sub-wordline driver SWD 30 are turned on for a period t3. The decoding signals WDi of a low level from the wordline drive decoder WDD 20 are transmitted to the subwordline SWL. For a period t4, both the first and second NMOS transistors N1 and N2 and the PMOS transistor P1 of the sub-wordline driver SWD 30 are turned on. The decoding signals WDi of a high level outputted from the wordline driver decoder WDD 20 are thus transmitted to the subwordline SWL.
Accordingly, the sub-wordline drivers SWD 30 respectively enable the sub-wordline SWL only when both the main decoding signal from the row decoder RD 10 and the decoding signals WDi from the wordline drive decoders 20 are at the high level. Considering one cell block in the background art as described above, since the main decoding signal MWL, the main decoding bar signal MWLb and the decoding signals WDi are designated in the same bank, the above signals remain inactive while one wordline is active.
On the other hand, when the wordline driver according to the background art is applied to a multi-bank memory (i.e., a single wordline drive decoder driving sub-wordline drivers with several banks), the wordline driver cannot be operative under this condition. In the multi-bank memory, a wordline may be independently enabled by each bank. Since the decoding signals WDi of the wordline drive decoder commonly share several banks, both the decoding signals WDi and the decoding signal MWL should be enabled at the high level in order to enable a wordline of the bank.
However, when the main decoding bar signal MWLb and the decoding signals WDi are enabled to operate a wordline of a second bank before disabling the wordline of the first bank after predetermined time, the decoding signals WDi of the first wordline drive decoder is disabled. Consequently, the wordline designated to the decoding signals WDi of the first wordline drive decoder is disabled and the wordline designated to the decoding signals WDi of the second wordline drive decoder is enabled, thereby damaging cell data.
Accordingly, when the wordline driver according to the background art is applied to the multi-bank memory, an additional control line should be provided to eliminate a damage in the cell data. Increases in chip size and power consumption for driving the wordline are unavoidable.